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- RM Core (status) (Mark S.)
- Issues
- New technology principles and policy hooks
- Differentiating underlying technology from features/functions/capabilities (e.g., SRIOV, PCI-PT, EPA, etc.)
- Principles: Abstraction breakage and custom s/w
- Principles: What level of h/w details can be exposed at various layers
- Hardware discussion continuation
- Storage configuration (10x 960GB vs. 3.2TB w/ 3x logical)
- DIMM distribution across sockets, memory controllers and buses
- NIC to socket mapping
- Physical interface assignment (E/W/OpenStack/Storage, N/S, PXE, OOB LOM)
- Hardware Objectives, Guidelines and Approach
- Guidelines vs. Requirements
- Objectives and Drivers for CNTT to specify h/w
- To what granularity
- Implications for RM Comp, RC and RI
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